Inputs to the STA tool
Dear readers, today we will be discussing the inputs needed for the STA tool and the importance of each input file and its contents. This will be a lengthy and informative presentation. I hope this learning is enjoyable for you all.
Inputs for the STA tool
1. Gate level netlist
2. SDC (Synopsys Design Constraints)
3. .Lib
4. SPEF (Standard Parasitic Exchange Format)
5. SDF (Standard Delay format)
1. Gate level netlist:
The tool will receive the netlist after routing as input. Our design information and its connections, including metals and vias, can be found here.
2. SDC
To ensure that the design meets its timing requirements, clock constraints are required in SDC. The contents of SDC include clock-related information such as clock period, clock latency, uncertainty, and transitions. And IO delay modelling like input and output delays, load, max fanout, max capacitance and max transition etc.., we will discuss the SDC contents in detail in the next post including the commands.
3. Lib:
.Lib contains the following information.
Cell Definitions:
- Logical Cells: Information about logical standard cells (gates, flip-flops, latches, etc.) and their functionality.
- I/O Cells: Definitions for input and output cells that interface with the external environment.
Timing Information:
- Cell Timing Models: Timing characteristics for each standard cell, including delays, transition times, setup times, hold times, etc.
- Library Constraints: Maximum and minimum input/output arrival times, clock-to-Q delays, and other timing constraints.
Power Information:
- Power Models: Power consumption information for each standard cell, including dynamic power, leakage power, and total power.
Physical Information:
- Cell Area Models: Information about the physical size or area of each standard cell.
- Pin Placement: Location and arrangement of pins for each cell.
Voltage and Temperature Dependencies:
- Voltage Scaling Information: How cell characteristics vary with different supply voltages.
- Temperature Scaling Information: How cell characteristics vary with different temperatures.
Library Constraints:
- Maximum Capacitance: Maximum allowable load capacitance for each cell.
- Maximum Fanout: Maximum number of loads a cell can drive.
Other Information:
- Library Version Information: Details about the library version and compatibility.
- Corner Models: Different corners representing best-case, typical, and worst-case scenarios for process variations.
- Please keep in mind that this is a simplified example for illustrative purposes, and the actual '.lib' files are much more detailed and complex.
- 4. SPEF :
- Here's a simplified example of what a SPEF file might look like:
* Unit: 1.0E-12 F, 1.0E+3 Ohms * Design Information Section D_NET 1 CLK * Node Information Section * Format: (node name) (node capacitance) (node resistance) * Units: F Ohms * Example: * R 1 1.0 * C 1 0.5 * Resistances and Capacitances Section * Format: (net name) (capacitance between nodes) (resistance between nodes) * Units: F Ohms * Example: * * 2 1.0 0.5
- To get a sense of how the SDF file would look, the following example is very basic. The actual file will be vast and complex.
- ;; Cell Timing Section
- (cell (cell_name)
- (cell_rise (condition) (timing_value))
- (cell_fall (condition) (timing_value))
- ; ... other cell timing information ...
- )
- ;; Pin Timing Section
- (pin (cell_name) (pin_name)
- (rise_capacitance (condition) (capacitance_value))
- (fall_capacitance (condition) (capacitance_value))
- ; ... other pin timing information ...
- )
- ;; Timing Checks Section
- (check (cell_name) (check_type) (limit_value))
- ; ... other timing checks ...
- ;; Port Transition Section
- (port (port_name) (clock_transition (rise|fall) (transition_value)))
- ; ... other port transition information ...
- ;; Interconnect Timing Section
- (interconnect (from_pin) (to_pin)
- (rise_delay (condition) (delay_value))
- (fall_delay (condition) (delay_value))
- ; ... other interconnect timing information ...
- )
- ;; Clock Section
- (clock (clock_name)
- (clock_type (primary|generated))
- (period (condition) (period_value))
- ; ... other clock information ...
- )
- ;; Clock Network Section
- (clock_network (clock_name)
- (hierarchical_pin_name (port_name))
- ; ... other clock network information ...
- )
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