SDC (Synopsys Design Constraints) contents part 4
Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as set_max_transition 0.5 UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack. set_max_capacitance 0.7 [all_nets] setting maximum capacitance of 700fF on all nets. similarly, set_
