SDC (Synopsys Design Constraints) contents
Dear readers, Today we will talk about the contents of the SDC, including commands. Concepts of skew, latency, uncertainty and more. However, since this might get lengthy, we will only cover a few of them here, covering the rest in later posts. Hope you guys have fun reading it.
In order to execute STA on the design, you will need to specify the clock for the flipflops and timing restrictions for all the ways in the design and all the ways out of the design.
Clock Attributes
1. create_clock
This creates a clock in the current design at the declared source and defines its period and waveform. The STA uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by this clock source. This is also called master clock.
Ex1: create_clock -period 10 -waveform{0 5} -name CLK [get_ports SCLK]
- name of the clock is CLK having period of 10ns with rising edge at 0ns and falling edge at 5ns is defined at the port SCLK. if -name is not specified then the clock name will be same as the port name.
Ex2: create_clock -period 4 -name VRCLK
- Above clock has no pins/ports associated with it, that type of clock is called virtual clock. Virtual clock physically does not exist, but it can be used to constrain the clock. It is used as a reference to constrain the interface pins.
2. create_generated_clock
For suppose if there is a divide-by-2 circuitry for a clock, then the time period of clock will change but STA does not know what the clock period in that case. So, we need to define these clocks as 'generated clocks'. Basically, generated clocks are derived from master clocks. It might be 'multiply-by' or 'divide-by' 1,2 3 etc.., and edge-shift options.
Ex1: create_generated_clock -divide_by 2 -name CLKDIV2 -source CLK [get_pins UPLL/CLKOUT]
- Here observe, generated clock named CLKDIV2 derived from CLK with period of 20ns is defined at the output of PLL . Note that 'multiply-by', 'divide-by' options referred to frequency of the clock. In this case frequency is divided by 2 means period will be doubled that is 20ns. At -source option we can give clock name or clock pin, both will work. below figure will give you a clear idea.
Another example for generated clock is
Ex2: create_generated_clock -divide_by 1 -name CLKDIV1 -source CLK [get_pins UAND1/Y].
-In the above example, the generated clock period is the same as the master clock period. Then you must have a doubt that do we need to generate another clock, if the clock period is same as the master clock, we can directly fed master clock to the flipflop? The answer is yes, we can create new master clock indeed. However, there are a few problems. See below example
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